With the development of the semiconductor industry, integrated circuits with higher performance and more powerful functions require greater element density. Thus, the sizes of the components need to be scaled further. The utilization of the core technology for 22 nanometers and beyond technology of integrated circuits has been the inevitable trend for the development of integrated circuits, which are also the projects for major international semiconductor companies and institutions to compete to develop. Study on CMOS device gate engineering with “high-k/metal gate” as the core technology is the most representative in 32/22 nanometer technology, and relevant studies on materials, processes and structures are conducted extensively. At present, the study on high-k gate dielectric/metal gate technology may comprise the gate-first process and the replacement gate process. In the gate-first process, the gate is formed before formation of the source and drain regions, while in the replacement gate process, of the gate is formed after formation of the source and drain regions. And in the replacement gate process, it is not necessary for the gate to be under high temperature for annealing.
For a MOS device with a high-k/metal gate structure, the quality of a high-k gate dielectric film and the interface property associated therewith directly affect the electrical properties of the device, especially the equivalent oxide thickness (EOT) and channel carrier mobility of the device. At present, in order to decrease EOT, the dielectric constant of the high-k gate dielectric material may be enhanced and the interface layer with low dielectric constant between the high-k gate dielectric and the semiconductor substrate may be thinned by optimization of the materials for the gate dielectric. With the continuous thinning of the interface layer, some atoms in the high-k gate dielectric material may be diffused into the channel region of the semiconductor substrate through the ultra-thin interface layer in high-temperature thermal treatment, which may disadvantageously degrade the carrier mobility of the channel region.
Therefore, in order to make compromise between the decrease of EOT and the degradation of carrier mobility of CMOSFET devices, there is a need for a new semiconductor device and a method of manufacturing the same.